Generally, integrated circuits will include multiple power domains. A device may, for instance, include an input/output (I/O) circuit along with a core circuit, each of which may be associated with a different power domain (e.g., the I/O circuit may be associated with a high voltage power domain, the core circuit may be associated with a low voltage power domain, etc.). Thus, signals may travel from a high voltage power domain to a low voltage power domain. Typically, from an electrostatic discharge (ESD) protection design point-of-view, one of the most critical issues of cross-domain interface circuits is gate oxide breakdown of low-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs). In addition, the overall gate oxide breakdown voltage (VBD) is decreasing in advancing technology. As such, any margin, for instance, between Vt1 (e.g., trigger voltage) of ESD grounded gate n-type MOS (ggNMOS) and VBD of MOSFET gate oxide is practically non-existent.
FIG. 1 schematically illustrates a circuit that includes a traditional cross-domain ESD protection scheme. As shown, the circuit in FIG. 1 includes an I/O input terminal 101 connected to transistors 103 and 105, the drains of which are connected to the gates of transistors 107 and 109. Moreover, the circuit includes design paths 111a (e.g., from power rail 113 to ground rail 115 through clamp 117, ground rail 119, and diode 121) and 111b (e.g., from power rail 113 to power rail 123 through clamp 117, ground rail 119, diode 121, ground rail 115, and a parasitic diode of clamp 125) to enable ESD current to travel, for instance, from VDD1 to VSS2 and VDD1 to VDD2. Nonetheless, some ESD current may also travel along path 127 through transistor 103 to damage the gate oxide of transistor 109 (e.g., under VDD1 to VSS2 ESD zapping), and along path 129 through transistor 103 to damage the gate oxide of transistor 107 (e.g., under VDD1 to VDD2 ESD zapping).
FIG. 2 schematically illustrates a typical solution for the problems of a traditional cross-domain ESD protection scheme. As shown, the circuit in FIG. 2 includes components similar to the components of the circuit in FIG. 1, such as transistors 201, 203, 205, and 207, power rails 209 and 211 (e.g., VDD1 and VDD2), ground rails 213 and 215 (e.g., VSS1 and VSS2), clamps 217 and 219, and diodes 221. To overcome some of the issues associated with the traditional cross-domain ESD protection scheme, the circuit in FIG. 2 further includes resistor 223, diode 225, and transistor 227 (e.g., grounded gate transistor). Resistor 223 reduces the voltage drop between the respective gate and source of transistors 205 and 207, decreasing the likelihood of gate oxide damage to transistors 205 and 207 as a result of an ESD event (e.g., ESD zapping). Diode 225 protects transistor 205 (e.g., PMOS transistor) from gate oxide breakdown during an ESD event from power rail 209 to power rail 211 (e.g., VDD1 to VDD2 ESD zapping). Transistor 227 protects transistor 207 (e.g., NMOS transistor) from gate oxide breakdown during an ESD event from power rail 209 to ground rail 215 (e.g., VDD1 to VSS2 ESD zapping).
Nonetheless, although the ESD protection scheme of FIG. 2 may increase gate-oxide protection in mature technologies, the scheme still has several drawbacks. For example, although resistor 223 reduces the voltage drop between the respective gate and source of the transistors 205 and 207, the inclusion of resistor 223 in the circuit negatively impacts high-speed I/O application. In addition, leakage may occur through diode 225 during normal operations (e.g., leakage may occur when VDD1 is powered on before VDD2 is powered on). While a power-on sequence may be implemented to mitigate leakage, such a solution hinders flexibility associated with the circuit. Furthermore, while the addition of transistor 227 may protect transistor 207 from gate oxide breakdown in mature technologies, such an approach will not be effective in advanced technologies, since any margin, for instance, between Vt1 of transistor 227 and VBD of the gate oxide of transistor 207 will practically be non-existent.
FIG. 3 schematically illustrates another solution for the problems of a traditional cross-domain ESD protection scheme. As shown, the circuit in FIG. 3 includes components similar to the components of the circuit in FIG. 1, such as transistors 301, 303, 305, and 307, power rails 309 and 311 (e.g., VDD1 and VDD2), ground rails 313 and 315 (e.g., VSS1 and VSS2), clamps 317 and 319, and diodes 321. To overcome some of the issues associated with the ESD protection schemes of FIGS. 1 and 2, the circuit in FIG. 3 includes resistors 323, 325, and 327, transistors 329 and 331, and source pump resistors 333 and 335. The addition of source pump resistors 333 and 335, for instance, further reduces the potential difference between the respective gate and source of the transistors 305 and 307, while the structure including resistor 327 and transistor 329 eliminates the need for a power-on sequence.
However, the ESD protection scheme of FIG. 3 also has several drawbacks. For example, as shown by indicator 337, transistor 331 may suffer false-triggering as a result of a noisy I/O ground rail 313 (e.g., simultaneous switching output and simultaneous switching noise (SSO/SSN)), resulting in distortion of the core output function. Moreover, the inclusion of source pump resistors 333 and 335 further reduces the speed of high-speed I/O applications and increases the design complexity of the circuit. In addition, the increase in the number of resistors (e.g., resistors 323, 325, and 327, and source pump resistors 333 and 335) results in more chip area required to implement the design, increasing the size of devices associated with such designs.
A need therefore exists for circuits with more effective ESD solutions, for instance, that complement high-speed I/O applications with minimal impact on device size, and enabling methodology.